Logic and computer design fundamentals. / (Record no. 7436)
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| fixed length control field | 04142nam a22002897a 4500 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20220316100330.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 120724t xxu||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781292096070 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 1292096071 |
| 040 ## - CATALOGING SOURCE | |
| Transcribing agency | LC |
| 050 ## - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | QA76.9.M28 |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Mano, M. Morris |
| 245 ## - TITLE STATEMENT | |
| Title | Logic and computer design fundamentals. / |
| Statement of responsibility, etc. | M. Morris Mano, Charles R. Kime, Tom Martin |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 5th ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | Boston: |
| Name of publisher, distributor, etc. | Pearson, |
| Date of publication, distribution, etc. | 2016. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 672 p: |
| Other physical details | ill.; |
| 440 ## - SERIES STATEMENT/ADDED ENTRY--TITLE | |
| Title | Always learning |
| 500 ## - GENERAL NOTE | |
| General note | Includes index. |
| 505 ## - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Overview: 1. Digital Systems and Information1-1 Information Representation1-2 Abstraction Layers in Computer Systems Design1-3 Number Systems1-4 Arithmetic Operations1-5 Decimal Codes1-6 Alphanumeric Codes1-7 Gray Codes1-8 Chapter Summary 2. Combinational Logic Circuits2-1 Binary Logic and Gates2-2 Boolean Algebra2-3 Standard Forms2-4 Two-Level Circuit Optimization2-5 Map Manipulation2-6 Exclusive-OR Operator and Gates2-7 Gate Propagation Delay2-8 Hardware Description Languages Overview2-9 HDL Representations-VHDL2-10 HDL Represenations-Verilog2-11 Chapter Summary 3. Combinational Logic Design3-1 Beginning Hierarchical Design3-2 Technology Mapping3-3 Combinational Functional Blocks3-4 Rudimentary Logic Functions3-5 Decoding3-6 Encoding3-7 Selecting3-8 Iterative Combinational Circuits3-9 Binary Adders3-10 Binary Subtraction3-11 Binary Adder-Subtractors3-12 Other Arithmetic Functions3-13 Chapter Summary 4. Sequential Circuits4-1 Sequential Circuit Definitions4-2 Latches4-3 Flip-Flops4-4 Sequential Circuit Analysis4-5 Sequential Circuit Design4-6 State-machine Diagrams and Applications4-7 HDL Representation for Sequential Circuits-VHDL4-8 HDL Representation for Sequential Circuits-Verilog4-9 Flip-Flop Timing4-10 Sequential Circuit Timing4-11 Asynchronous Interactions4-12 Synchronization and Metastability4-13 Synchronous Circuit Pitfalls4-14 Chapter Summary 5. Digital Hardware Implementation5-1 The Design Space5-2 Programmable Implementation Technologies5-3 Chapter Summary 6. Registers and Register Transfers6-1 Registers and Load Enable6-2 Register Transfers6-3 Register Transfer Operations6-4 Register Transfers in VHDL and Verilog6-5 Microoperations6-6 Microoperations on a Single Register6-7 Register-Cell Design6-8 Multiplexer and Bus-Baed Transfers for Multiple Registers6-9 Serial Transfer and Microoperations6-10 Control of Register Transfers6-11 HDL Representation for Shift Registers and Counters-VHDL6-12 HDL Representation for Shift Registers and Counters-Verilog6-13 Microprogrammed Control6-15 Chapter Summary 7. Memory Basics7-1 Memory Definitions7-2 Random-Access Memory7-3 SRAM Integrated Circuits7-4 Array of SRAM ICs7-5 DRAM ICs7-6 DRAM Types7-7 Arrays of Dynamic RAM ICs7-8 Chapter Summary 8. Computer Design Basics8-1 Computer Design Basics8-2 Datapaths8-3 The Arithmetic/Logic Unit8-4 The Shifter8-5 Datapath Representation8-6 The Control Word8-7 A Simple Computer Architecture8-8 Single-Cycle Hardwired Control8-9 Multiple-Cycle Hardwired Control8-10 Chapter Summary 9. Instruction Set Architecture9-1 Computer Architecture Concepts9-2 Operand Addressing9-3 Addressing Modes9-4 Instruction Set Architectures9-5 Data-Transfer Instructions9-6 Data-Manipulation Instructions9-7 Floating-Point Computations9-8 Program Control Instructions9-9 Program Interrupt9-10 Chapter Summary 10. RISC and CISC Processors10-1 Pipelined Datapath10-2 Pipelined Control10-3 The Reduced Instruction Set Computer10-4 The Complex Instruction Set Computer10-5 More on Design10-6 Chapter Summary 11. Input-Output and Communication11-1 Computer I/O11-2 Sample Peripherals11-3 I/O Interfaces11-4 Serial Communication11-5 Modes of Transfer11-6 Priority Interrupt11-7 Direct Memory Access11-8 Chapter Summary 12. Memory Systems12-1 Memory Hierarchy12-2 Locality of Reference12-3 Cache Memory12-4 Virtual Memory12-5 Chapter Summary |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Electronic digital computers -- Circuits. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Logic circuits. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Logic design. |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Kime, Charles R. |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Martin, Tom |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | |
| Koha item type | Books |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Permanent location | Current location | Shelving location | Date acquired | Full call number | Barcode | Date last seen | Price effective from | Koha item type |
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| WISCONSIN INTERNATIONAL UNIVERSITY COLLEGE, GHANA KUMASI LIBRARY | WISCONSIN INTERNATIONAL UNIVERSITY COLLEGE, GHANA KUMASI LIBRARY | General Stacks | 15/11/2019 | QA76.9.M28(5e) | K/2426/2426/19 | 06/07/2020 | 06/07/2020 | Books |